In the fabrication of integrated circuits, the degree of integration of a dynamic random access memory (DRAM) may be limited by a decrease of memory cell capacitance resulting from a decrease in the area of a memory cell. A decrease in cell capacitance may also hinder the low-voltage operation of a memory cell. Further, decreases in capacitance may deteriorate the reading performance of the memory cell and increase the soft error rate (SER). Therefore, it would be desirable to increase the integration of semiconductor memory devices without decreasing memory cell capacitance.
As a result, capacitors having three-dimensional structures have been proposed to increase memory cell capacitance. As an Example, FIGS. 1 to 3 are cross-sectional views illustrating a method according to the prior art for forming a capacitor having a box-shaped lower electrode according to the prior art.
Referring to FIG. 1, an interlayer dielectric layer 20 and an etching stop layer 30 are sequentially formed on a semiconductor substrate 10. The interlayer dielectric layer 20 and the etching stop layer 30 can be respectively formed from borophosphosilicate glass (BPSG) and silicon nitride (Si.sub.3 N.sub.4).
Referring to FIG. 2, an etching stop layer pattern 30a and an interlayer dielectric layer pattern 20a, each having an aligned contact hole exposing a predetermined region of the semiconductor substrate 10, are formed by patterning the etching stop layer 30 and the interlayer dielectric layer 20, respectively. A conductive layer 40, such as a doped polysilicon layer, is then formed on the etching stop layer filling the contact hole.
Referring to FIG. 3, a lower electrode 40a is formed by patterning the conductive layer 40 to expose the etching stop layer pattern 30a using a photoresist pattern (not shown) as an etching mask. Next, a dielectric layer 50, such as an ONO (SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2) layer, is formed on the lower electrode 40a and the etching stop layer pattern 30a. An upper electrode 60 is then formed by depositing a conductive material on the dielectric layer.
In accordance with the above-described method for fabricating a capacitor for an integrated circuit, the thickness of the lower electrode 40a is typically increased to increase the surface area of the electrode, thereby increasing cell capacitance. The thicker lower electrode may, however, increase a step between the cell array region and a peripheral circuit region. As a result, the patterns and step coverage may deteriorate during subsequent processing steps, such as metallization.